A technician has installed an additional CPU into a server, but now the server is failing to pass POST. After verifying the CPU speed and multiplier, which of the following does the technician need…

ECC (Error Correcting Code) is a memory subsystem feature governing how RAM handles bit errors; it has no direct relationship to CPU-to-CPU compatibility or to POST failures introduced by adding a second processor.

CAS (Column Address Strobe) latency is a DRAM timing parameter that affects memory controller operation; it is unrelated to whether two physical CPUs are compatible with each other in a dual-socket configuration.

CPU stepping identifies the exact silicon revision of a processor die, and multi-processor server platforms require all CPUs to share the same stepping so firmware and the processor interconnect fabric can coordinate correctly. After confirming matching speed and multiplier, stepping is the next critical compatibility variable to verify because even processors with the same model number can ship at different steppings that are incompatible in an MP configuration.

Bus size is dictated by the CPU architecture and socket specification, both of which are already implicitly validated when speed and multiplier match; it is not an independent variable that causes POST failure when populating a second CPU socket.