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SK0-004 · Question #346

Which of the following defines memory interleaving?

The correct answer is B. The distribution of data written across all the memory DIMMs in one bank. Memory interleaving distributes data across all DIMMs within a single memory bank so consecutive memory addresses reside on different modules, enabling overlapping access cycles and higher effective bandwidth.

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Question

Which of the following defines memory interleaving?

Options

  • AThe distribution of data written across all the memory DIMMs and the L1 cache
  • BThe distribution of data written across all the memory DIMMs in one bank
  • CThe distribution of data written across all the memory DIMMs and the processor
  • DThe distribution of data written across all the memory DIMMs and the L2 cache

How the community answered

(30 responses)
  • A
    3% (1)
  • B
    87% (26)
  • C
    3% (1)
  • D
    7% (2)

Why each option

Memory interleaving distributes data across all DIMMs within a single memory bank so consecutive memory addresses reside on different modules, enabling overlapping access cycles and higher effective bandwidth.

AThe distribution of data written across all the memory DIMMs and the L1 cache

The L1 cache is an on-die processor cache and is entirely separate from the DIMM-level interleaving mechanism, which operates only within main system memory.

BThe distribution of data written across all the memory DIMMs in one bankCorrect

Memory interleaving works by spreading sequential memory addresses across multiple physical DIMM modules within one bank, so the memory controller can pipeline read and write operations - accessing the next module while the previous one is still completing its cycle - which reduces latency and increases overall memory throughput.

CThe distribution of data written across all the memory DIMMs and the processor

The processor is not a target in memory interleaving; the technique distributes data among memory modules in a bank, not between DIMMs and the CPU itself.

DThe distribution of data written across all the memory DIMMs and the L2 cache

The L2 cache, like L1, is a processor or chipset-level cache and is not involved in memory interleaving, which is purely a main memory controller function.

Concept tested: Memory interleaving across DIMMs in a single bank

Source: https://www.intel.com/content/www/us/en/support/articles/000005738/boards-and-kits.html

Topics

#memory interleaving#DIMM#memory bank#memory performance

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