Refer to the exhibit: Which operation is represented?

Question

Exhibit

Options

• AWrite-through wrong
• BRead Hit
• CRead Miss
• DWrite-back

• A
  5% (2)
• B
  15% (6)
• C
  76% (31)
• D
  5% (2)

Explanation

Option C is correct because a Read Miss occurs when the CPU requests data from cache and the data is not present, forcing the system to retrieve it from slower main memory and load it into cache before the CPU can use it - exactly the two-step fetch process typically shown in such exhibits. A Read Hit (B) is the opposite scenario: the data is found in cache on the first check, so no main memory access is needed. Write-through (A) is a write policy, not a read operation - it describes writing data to both cache and main memory simultaneously on every store. Write-back (D) is also a write policy, where data is written only to cache and deferred to main memory later when that cache line is evicted.

Memory tip: Pair the words literally - "Read" tells you the CPU is fetching data, and "Miss" tells you the cache lookup failed. If both things are true (fetch + failure), it is a Read Miss.

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