D-ISM-FN-01 · Question #180
Which operation is represented in the exhibit?
The correct answer is B. Read Cache Miss. Option B is correct because a Read Cache Miss occurs when the CPU requests data, checks the cache first, fails to find it there, and must then retrieve it from main memory - the exhibit likely shows this two-step lookup: cache check → fallback to RAM, with the data subsequently…
Question
Which operation is represented in the exhibit?
Exhibit
Options
- AWrite-back Cache
- BRead Cache Miss
- CWrite-through Cache
- DRead Cache Hit
How the community answered
(30 responses)- A7% (2)
- B73% (22)
- C17% (5)
- D3% (1)
Explanation
Option B is correct because a Read Cache Miss occurs when the CPU requests data, checks the cache first, fails to find it there, and must then retrieve it from main memory - the exhibit likely shows this two-step lookup: cache check → fallback to RAM, with the data subsequently loaded into the cache.
Why the distractors are wrong:
- A (Write-back Cache): A write-back operation involves writing data to the cache first and only updating main memory later; no read request is involved.
- C (Write-through Cache): Write-through writes data to both cache and main memory simultaneously on every write - again, this is a write operation, not a read.
- D (Read Cache Hit): A cache hit means the requested data was found in the cache, so no memory access is needed - the opposite of what the exhibit shows.
Memory tip: Think of the cache like a sticky note on your desk. A Hit means the answer is already on the note (fast). A Miss means you have to dig through your filing cabinet (slow) - and then you write it on the sticky note so next time is faster.
Topics
Community Discussion
No community discussion yet for this question.
