117-201 · Question #307
When a makefile is included in a source code package, what are commonly defined targets in the file?
The correct answer is B. clean, install, uninstall. See the full explanation below for the reasoning.
Question
Options
- ACFLAGS, CPPFLAGS, LIBS, LDFLAGS
- Bclean, install, uninstall
- CPATHS, DESTDIR, LIBS, LDFLAGS
- Dprefix, exec_prefix, bindir, mandir
How the community answered
(34 responses)- A6% (2)
- B74% (25)
- C18% (6)
- D3% (1)
Community Discussion
5
Wesley A.Dec 4, 2025B is the right answer. Targets like clean, install, and uninstall are the standard actions you invoke with the make command, not variables, so that is what separates them from all the other options which list variable names used to configure the build, not targets you actually run.
Yusuf A.Nov 19, 2025Saw this exact one on my exam, remembered "make clean" from cleaning up a broken build at work, picked B no hesitation.
Orla P.Dec 15, 2025Targets are the actions you tell make to run, and clean, install, uninstall show up in almost every open source Makefile you will ever touch. On my actual 117-201 sitting I almost second-guessed myself because A looks tempting if you are thinking about variables you set before compiling, but variables and targets are two different things, and once I remembered that distinction the answer was obvious.
Yusuf A.Dec 16, 2025Solid point on the variable versus target distinction, and worth adding that clean is actually just a convention with no built-in meaning to make itself, so a poorly written Makefile could technically omit it or name it something else, which is why the LPI objectives stress recognizing the standard set.
Nina C.Nov 29, 2025So I went with B because clean, install, and uninstall sound like actual actions you would type after make, not settings the compiler reads, but I am still working out the difference. Are the items in the other options considered variables or macros rather than targets, and is that the main distinction the exam wants us to recognize here?